/***********************************************************************************************************
 * Copyright (c)  2017 - 2022, Unicmicro Co.,Ltd .
 * All rights reserved.
 * Filename    : um321xF.h
 * Description : um321xF addr header file
 * Author(s)   : will
 * version     : V1.0
 * Modify date : 2022-07-10
 ***********************************************************************************************************/
#ifndef __UM321XF_H__
#define __UM321XF_H__

#undef NULL
#define NULL 0                   /* see <stddef.h> */

/* --------------------  Configuration of the Cortex-M0 Processor and Core Peripherals  ------------------ */
#define __CM0_REV                 					0x0000U   												/* Core revision r0p0 */
#define __MPU_PRESENT             					0         												/* MPU present or not */
#define __VTOR_PRESENT            					0         												/* no VTOR present*/
#define __NVIC_PRIO_BITS          					2         												/* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig    					0         												/* Set to 1 if different SysTick Config is used */

/* ------------------------------  Interrupt Number Definition  ------------------------------------------ */
typedef enum IRQn
{
	/* --------------------------  Cortex-M0 Processor Exceptions Numbers  ------------------------------- */
	NonMaskableInt_IRQn			  					= -14,      											/* 2 Non Maskable Interrupt */
	HardFault_IRQn                					= -13,      											/* 3 HardFault Interrupt */
	SVCall_IRQn                   					= -5,      												/* 11 SV Call Interrupt */
	PendSV_IRQn                   					= -2,      												/* 14 Pend SV Interrupt */
	SysTick_IRQn                  					= -1,      												/* 15 System Tick Interrupt */

	/* --------------------------  ARMCM0 Specific Interrupt Numbers  ------------------------------------ */
	GPIO_PA_IRQn				  					= 0,        											/* 0:  GPIO_PA_IRQHandler */
	GPIO_PB_IRQn				  					= 1,        											/* 1:  GPIO_PB_IRQHandler */
	GPIO_PC_IRQn				  					= 2,        											/* 2:  GPIO_PC_IRQHandler */
	GPIO_PD_IRQn		          					= 3,        											/* 3:  GPIO_PD_IRQHandler */
	DMA_IRQn		          	  					= 4,        											/* 4:  DMA_IRQHandler */
	LPTIMER23_IRQn                    				= 5,        											/* 5:  LPTIMER23_IRQHandler */
	UART0_IRQn                    					= 6,        											/* 6:  UART0_IRQHandler */
	LPUART_IRQn	                  					= 7,        											/* 7:  LPUART_IRQHandler */
	UART1_IRQn                    					= 8,        											/* 8:  UART1_IRQHandler */
	I2C0_IRQn                      					= 9,        											/* 9:  I2C0_IRQHandler */
	SPI0_IRQn                     					= 10,       											/* 10: SPI0_IRQHandler */
	SPI1_IRQn                     					= 11,       											/* 11: SPI1_IRQHandler */
	CAN_IRQn                     					= 12,       											/* 12: CAN_IRQHandler */
	GPIO_PF_IRQn                     				= 13,       											/* 13: GPIO_PF_IRQHandler */    
	GTIMER0_IRQn		          					= 14,       											/* 14: GTIMER0_IRQHandler */
	GTIMER1_IRQn	              					= 15,       											/* 15: GTIMER1_IRQHandler */
	GTIMER2_IRQn	              					= 16,       											/* 16: GTIMER2_IRQHandler */
	QSPI_IRQn                  						= 17,       											/* 17: QSPI_IRQHandler */
	LPTIMER01_IRQn                  				= 18,       											/* 18: LPTIMER01_IRQHandler */	 
	ANALOG_IRQn                  					= 19,       											/* 19: ANALOG_IRQHandler */	
	GPIO_PE_IRQn                  					= 20,       											/* 20: GPIO_PE_IRQHandler */	
	ATIMER_IRQn                  					= 21,       											/* 21: ATIMER_IRQHandler */	    
	WDT_IRQn                  	  					= 22,       											/* 22: WDT_IRQHandler */
	RTC_IRQn                  	  					= 23,       											/* 23: RTC_IRQHandler */
	ADC_IRQn                      					= 24,       											/* 24: ADC_IRQHandler */
	BTIMER01_IRQn                    				= 25,        											/* 25: BTIMER0_IRQHandler */
	I2C1_IRQn                    				   	= 26,        											/* 26: I2C1_IRQHandler */
	WWDT_IRQn                    					= 27,        											/* 27: WWDT_IRQHandler */
	UART2_IRQn                 	  					= 28,       											/* 28: UART2_IRQHandler */
	BTIMER23_IRQn                 	  				= 29,       											/* 29: BTIMER1_IRQHandler */
	FLASH_IRQn                    					= 30,        											/* 30: FLASH_IRQHandler */
	GPIO_PG_IRQn                   					= 31        											/* 31: GPIO_PG_IRQHandler */
} IRQn_Type;

#include  "core_cm0plus.h"

/***********************************************************************************************************/
/*                            Device Specific Peripheral Section                                           */
/***********************************************************************************************************/

/*------------------------------------------------- EFC ---------------------------------------------------*/
#define EFC_BASE_ADDR								0x01100000
#define REG_EFC_CTRL    							(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x00))		/* EFC ���ƼĴ��� */
#define REG_EFC_SEC    								(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x04))		/* EFC д����ȫ�Ĵ��� */
#define REG_EFC_STATUS    							(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x08))		/* EFC ״̬�Ĵ��� */
#define REG_EFC_INTSTATUS   						(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x0C))		/* EFC �ж�״̬�Ĵ��� */
#define REG_EFC_INEN   								(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x10))		/* EFC �ж�ʹ�ܼĴ��� */
#define REG_EFC_HALFUS   							(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x14))		/* EFC ʱ���߼Ĵ��� */
#define REG_EFC_RCHTRIM   							(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x20))		/* EFC RCH TRIM �Ĵ��� */
#define REG_EFC_RCLTRIM   							(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x24))		/* EFC RCL TRIM �Ĵ��� */
#define REG_EFC_LDOTRIM   							(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x28))		/* EFC LDO TRIM �Ĵ��� */
#define REG_EFC_VREFTRIM   							(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x2C))		/* EFC VREF TRIM �Ĵ��� */
#define REG_EFC_OPATRIM   							(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x30))		/* EFC OPA TRIM �Ĵ��� */
#define REG_EFC_COMP0TRIM   						(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x34))		/* EFC COMP0 TRIM �Ĵ��� */
#define REG_EFC_COMP1TRIM   						(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x38))		/* EFC COMP1 TRIM �Ĵ��� */
#define REG_EFC_COMP2TRIM   						(*(volatile uint32_t *)(EFC_BASE_ADDR + 0x3C))		/* EFC COMP2 TRIM �Ĵ��� */

/*------------------------------------------------- QSPI --------------------------------------------------*/
#define QSPI_BASE_ADDR								0x01100400
#define REG_QSPI_CTRL          					    (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x00))		/* SPI ���üĴ��� */
#define REG_QSPI_BAUD            					(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x04))		/* SPI ���������üĴ��� */
#define REG_QSPI_MEMO_ACC            				(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x08))		/* SPI �洢���������üĴ��� */
#define REG_QSPI_CMD          					    (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x0C))		/* SPI ����Ĵ��� */
#define REG_QSPI_PARA_R          					(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x10))		/* SPI �������Ĵ��� */
#define REG_QSPI_PARA_W           				  	(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x14))		/* SPI д�����Ĵ��� */
#define REG_QSPI_PGT_SET           				  	(*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x18))		/* SPI ��дʱ�����üĴ��� */
#define REG_QSPI_INTEN      				        (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x1C))		/* SPI �ж�ʹ�ܿ��ƼĴ��� */
#define REG_QSPI_INTUS      				        (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x20))		/* SPI �ж�״̬�Ĵ��� */
#define REG_QSPI_STATUS      				        (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x24))		/* SPI ״̬�Ĵ��� */
#define REG_QSPI_RXBUF      				        (*(volatile uint32_t *)(QSPI_BASE_ADDR + 0x28))		/* SPI ���ջ���Ĵ��� */

/*------------------------------------------------- UART0 -------------------------------------------------*/
#define UART0_BASE_ADDR								0x40000000
#define REG_UART0_ISR								(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x00))	/* UART0 �ж�״̬�Ĵ��� */
#define REG_UART0_IER								(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x04))	/* UART0 �ж�ʹ�ܼĴ��� */
#define REG_UART0_CR								(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x08))	/* UART0 ���ƼĴ��� */
#define REG_UART0_TDR								(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x0C))	/* UART0 �������ݼĴ��� */
#define REG_UART0_RDR								(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x0C))	/* UART0 �������ݼĴ��� */
#define REG_UART0_BRPL								(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x10))	/* UART0 �����ʲ�����λ�Ĵ��� */
#define REG_UART0_BRPH								(*(volatile uint32_t *)(UART0_BASE_ADDR + 0x14))	/* UART0 �����ʲ�����λ�Ĵ��� */

/*------------------------------------------------ LPUART -------------------------------------------------*/
#define LPUART_BASE_ADDR							0x40000400
#define REG_LPUART_LPURXD							(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x00))	/* LPUART �������ݼĴ��� */
#define REG_LPUART_LPUTXD							(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x04))	/* LPUART �������ݼĴ��� */
#define REG_LPUART_LPUSTA							(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x08))	/* LPUART ״̬�Ĵ��� */
#define REG_LPUART_LPUCON							(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x0C))	/* LPUART ���ƼĴ��� */
#define REG_LPUART_LPUIF							(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x10))	/* LPUART �жϱ�־�Ĵ��� */
#define REG_LPUART_LPUBAUD							(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x14))	/* LPUART �����ʼĴ��� */
#define REG_LPUART_LPUEN							(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x18))	/* LPUART ����ʹ�ܼĴ��� */
#define REG_LPUART_COMPARE							(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x1C))	/* LPUART ����ƥ��Ĵ��� */
#define REG_LPUART_MCTL								(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x20))	/* LPUART �����ʵ��ƿ��ƼĴ��� */
#define REG_LPUART_WKCKE							(*(volatile uint32_t *)(LPUART_BASE_ADDR + 0x24))	/* LPUART ƥ���жϻ��ѼĴ��� */

/*------------------------------------------------- SPI0 --------------------------------------------------*/
#define SPI0_BASE_ADDR								0x40000800
#define REG_SPI0_SPICR          					(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x00))		/* SPI0 ���üĴ��� */
#define REG_SPI0_SPICS0            					(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x04))		/* SPI0 ��ģʽ���ƼĴ���0 */
#define REG_SPI0_SPICS1             				(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x08))		/* SPI0 ��ģʽ���ƼĴ���1 */
#define REG_SPI0_SPIOPCR            				(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x14))		/* SPI0 ���̿��ƼĴ��� */
#define REG_SPI0_SPIIE          					(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x18))		/* SPI0 �жϿ��ƼĴ��� */
#define REG_SPI0_SPIIF          					(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x1C))		/* SPI0 �жϱ�־�Ĵ��� */
#define REG_SPI0_SPITXBUF           				(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x20))		/* SPI0 ���ͻ���Ĵ��� */
#define REG_SPI0_SPIRXBUF           				(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x24))		/* SPI0 ���ջ���Ĵ��� */
#define REG_SPI0_DMA_SPIRX_LEV      				(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x28))		/* SPI0 DMA�������üĴ��� */
#define REG_SPI0_DMA_SPITX_LEV      				(*(volatile uint32_t *)(SPI0_BASE_ADDR + 0x2C))		/* SPI0 DMA�������üĴ��� */

/*------------------------------------------------- GTIMER0 ------------------------------------------------*/
#define GTIMER0_BASE_ADDR							0x40000C00
#define REG_GTIM0_CR								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x00))	/* Timer0 ���ƼĴ��� */	
#define REG_GTIM0_IER								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x04))	/* Timer0 �ж�ʹ�ܼĴ��� */
#define REG_GTIM0_SR								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x08))	/* Timer0 ״̬�Ĵ��� */
#define REG_GTIM0_EGR								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x0C))	/* Timer0 �¼������Ĵ��� */
#define REG_GTIM0_CCMR								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x10))	/* Timer0 ��׽/�ȽϼĴ��� */
#define REG_GTIM0_CCER								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x14))	/* Timer0 ��׽/�Ƚ�ʹ�ܼĴ��� */
#define REG_GTIM0_CNT								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x18))	/* Timer0 �������Ĵ��� */
#define REG_GTIM0_PSC								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x1C))	/* Timer0 Ԥ��Ƶ�Ĵ��� */
#define REG_GTIM0_ARR								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x20))	/* Timer0 �Զ����ؼĴ��� */
#define REG_GTIM0_CCR								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x24))	/* Timer0 ��׽/�ȽϼĴ��� */
#define REG_GTIM0_CARS1								(*(volatile uint32_t *)(GTIMER0_BASE_ADDR + 0x28))	/* Timer0 ��׽/�ȽϼĴ��� */ 

/*------------------------------------------------- LPTIMER01 -----------------------------------------------*/
#define LPTIMER01_BASE_ADDR							0x40001000
#define REG_LPTIM0_CR1								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x00))	/* LPTIM0 ���ƼĴ���1 */
#define REG_LPTIM0_CR2								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x04))	/* LPTIM0 ���ƼĴ���2 */
#define REG_LPTIM01_IER								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x08))	/* LPTIM01 �ж�ʹ�ܼĴ��� */
#define REG_LPTIM01_SR								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x0C))	/* LPTIM01 �жϱ�־�Ĵ��� */
#define REG_LPTIM0_CNT1								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x10))	/* LPTIM0 ����ֵ�Ĵ��� */
#define REG_LPTIM0_CCMCFG1							(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x14))	/* LPTIM0 ��׽�Ƚ����üĴ���1 */
#define REG_LPTIM0_CCMCFG2							(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x18))	/* LPTIM0 ��׽�Ƚ����üĴ���2 */
#define REG_LPTIM0_ARR1								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x1C))	/* LPTIM0 �Զ���װ�ؼĴ��� */
#define REG_LPTIM0_CCR1								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x20))	/* LPTIM0 ��׽�ȽϼĴ���1 */
#define REG_LPTIM0_CCR2								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x24))	/* LPTIM0 ��׽�ȽϼĴ���2 */
#define REG_LPTIM0_LOAD1							(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x28))	/* LPTIM0 ����ֵload�Ĵ��� */
#define REG_LPTIM0_BUFFER1							(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x2C))	/* LPTIM0 ��������Ĵ��� */
#define REG_LPTIM1_CR3								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x30))	/* LPTIM1 ���ƼĴ���1 */
#define REG_LPTIM1_CR4								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x34))	/* LPTIM1 ���ƼĴ���2 */
#define REG_LPTIM1_CNT2								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x38))	/* LPTIM1 �ж�ʹ�ܼĴ��� */
#define REG_LPTIM1_CCMCFG3							(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x3C))	/* LPTIM1 �жϱ�־�Ĵ��� */
#define REG_LPTIM1_CCMCFG4							(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x40))	/* LPTIM1 ����ֵ�Ĵ��� */
#define REG_LPTIM1_ARR2								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x44))	/* LPTIM1 ��׽�Ƚ����üĴ���1 */
#define REG_LPTIM1_CCR3								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x48))	/* LPTIM1 ��׽�Ƚ����üĴ���2 */
#define REG_LPTIM1_CCR4								(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x4C))	/* LPTIM1 �Զ���װ�ؼĴ��� */
#define REG_LPTIM1_LOAD2							(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x50))	/* LPTIM1 ����ֵload�Ĵ��� */
#define REG_LPTIM1_BUFFER2							(*(volatile uint32_t *)(LPTIMER01_BASE_ADDR + 0x54))	/* LPTIM1 ��������Ĵ��� */

/*------------------------------------------------- RTC ---------------------------------------------------*/
#define RTC_BASE_ADDR								0x40001400
#define REG_RTC_RTCWE                  				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x00))		/* RTC дʹ�ܼĴ��� */
#define REG_RTC_RTCIE                  				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x04))		/* RTC �ж�ʹ�ܼĴ��� */
#define REG_RTC_RTCIF                  				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x08))		/* RTC �жϱ�־�Ĵ��� */
#define REG_RTC_BCDSEC                  			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x0C))		/* RTC BCDʱ����Ĵ��� */
#define REG_RTC_BCDMIN             					(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x10))		/* RTC BCDʱ����ӼĴ��� */
#define REG_RTC_BCDHOUR                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x14))		/* RTC BCDʱ��Сʱ�Ĵ��� */
#define REG_RTC_BCDDATE             				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x18))		/* RTC BCDʱ����Ĵ��� */
#define REG_RTC_BCDWEEK                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x1C))		/* RTC BCDʱ�����ڼĴ��� */
#define REG_RTC_BCDMONTH                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x20))		/* RTC BCDʱ���¼Ĵ��� */
#define REG_RTC_BCDYEAR                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x24))		/* RTC BCDʱ����Ĵ��� */
#define REG_RTC_ALARM                 				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x28))		/* RTC ���ӼĴ��� */
#define REG_RTC_FSEL                 				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x2C))		/* RTC ʱ���ź�������ƼĴ��� */
#define REG_RTC_ADJUST                 				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x30))		/* RTC LTBC��ֵ�����Ĵ��� */
#define REG_RTC_ADSIGN                 				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x34))		/* RTC LTBC��ֵ��������Ĵ��� */	
#define REG_RTC_PRISEN                 				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x38))		/* RTC LTBC�����Уʹ�ܼĴ��� */
#define REG_RTC_SECCNT                 				(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x3C))		/* RTC ��������Ĵ��� */
#define REG_RTC_STAMPEN                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x40))		/* RTC ʱ���ʹ�ܼĴ��� */
#define REG_RTC_CLKSTAMP0R                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x44))		/* RTC ������ʱ����Ĵ���0 */
#define REG_RTC_CALSTAMP0R                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x48))		/* RTC �������������Ĵ���0 */
#define REG_RTC_CLKSTAMP0F                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x4C))		/* RTC �½���ʱ����Ĵ���0 */	
#define REG_RTC_CALSTAMP0F                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x50))		/* RTC �½����������Ĵ���0 */
#define REG_RTC_CLKSTAMP1R                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x54))		/* RTC ������ʱ����Ĵ���1 */
#define REG_RTC_CALSTAMP1R                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x58))      /* RTC �������������Ĵ���1 */
#define REG_RTC_CLKSTAMP1F                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x5C))      /* RTC �½���ʱ����Ĵ���1 */
#define REG_RTC_CALSTAMP1F                 			(*(volatile uint32_t *)(RTC_BASE_ADDR + 0x60))      /* RTC �½����������Ĵ���1 */

/*------------------------------------------------- CRC ---------------------------------------------------*/
#define CRC16_BASE_ADDR								0x40001800
#define REG_CRC16_DATA              				(*(volatile uint32_t *)(CRC16_BASE_ADDR + 0x00))	/* CRC���ݼĴ��� */
#define REG_CRC16_INIT              				(*(volatile uint32_t *)(CRC16_BASE_ADDR + 0x04))	/* CRC��ʼֵ�Ĵ��� */
#define REG_CRC16_CTRL              				(*(volatile uint32_t *)(CRC16_BASE_ADDR + 0x08))	/* CRC���ƼĴ��� */

/*------------------------------------------------- ADC ----------------------------------------------*/
#define ADC_0										0
#define ADC_1										1
#define ADC_2										2
#define ADC_3										3
#define ADC_4										4
#define ADC_5										5
#define ADC_6										6
#define ADC_7										7
#define ADC_8										8
#define ADC_9										9
#define ADC_10										10
#define ADC_11										11
#define ADC_12										12
#define ADC_13										13

#define ADC_BASE_ADDR								0x40001C00
#define REG_ADC_GCR                  				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x00))		/*ADC �ܿؼĴ��� */
#define REG_ADC_DR(x)								(*(volatile uint32_t *)(ADC_BASE_ADDR + (0x04*(x)+0x04) ))		/*ADC ͨ��x���ݼĴ��� */
#define REG_ADC_CDR                  				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x3C))		/*ADC ʱ�ӷ�Ƶ�Ĵ��� */
#define REG_ADC_ISR                  				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x40))		/*ADC �ж�״̬�Ĵ��� */
#define REG_ADC_IER                  				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x44))		/*ADC �ж�ʹ�ܼĴ��� */
#define REG_ADC_ICR                  				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x48))		/*ADC �ж�����Ĵ��� */
#define REG_ADC_COUNT                				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x4C))		/*ADC ת������Ĵ��� */
#define REG_ADC_RXREG                				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x50))		/*ADC �������ݼĴ��� */
#define REG_ADC_CSTAT                				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x54))		/*ADC ״̬�Ĵ��� */
#define REG_ADC_SPW		             				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x58))		/*ADC ����ʱ�������Ĵ��� */
#define REG_ADC_TCRL		             			(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x5C))		/*ADC ģ�����üĴ��� */
#define REG_ADC_HDT		             				(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x60))		/*ADC Ӳ������ʹ�����üĴ��� */	
#define REG_ADC_HDSET0		             			(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x64))		/*ADC Ӳ������ʹ�����üĴ���0 */		
#define REG_ADC_HDSET1		             			(*(volatile uint32_t *)(ADC_BASE_ADDR + 0x68))		/*ADC Ӳ������ʹ�����üĴ���1 */	

/*------------------------------------------------- SYSREG ------------------------------------------------*/
#define SCU_BASE_ADDR								0x40002000
#define REG_SCU_CTRL0								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x00))		/* ϵͳ���ƼĴ���0 */
#define REG_SCU_CTRL1								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x04))		/* ϵͳ���ƼĴ���1 */
#define REG_SCU_CTRLPROTECT							(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x08))		/* ϵͳ���Ʊ����Ĵ��� */
#define REG_SCU_OSCCTRL								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x0C))		/* ʱ�ӿ��ƼĴ��� */
#define REG_SCU_PERICLKEN							(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x10))		/* ��Χģ��ʱ�ӼĴ��� */
#define REG_SCU_RESETFLAG							(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x20))		/* ��λ��ʶ�Ĵ��� */
#define REG_SCU_PERIRESET							(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x24))		/* ��Χģ�鸴λ���ƼĴ��� */
#define REG_SCU_EXTRESETCTRL						(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x28))		/* �ⲿ��λ�˲����ƼĴ��� */
#define REG_SCU_PASEL								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x30))		/* �˿�PA�������üĴ��� */
#define REG_SCU_PBSEL								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x34))		/* �˿�PB�������üĴ��� */
#define REG_SCU_PCSEL								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x38))		/* �˿�PC�������üĴ��� */
#define REG_SCU_PDSEL								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x3C))		/* �˿�PD�������üĴ��� */
#define REG_SCU_PESEL								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x40))      /* �˿�PE�������üĴ��� */
#define REG_SCU_PFSEL								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x44))      /* �˿�PF�������üĴ��� */
#define REG_SCU_PGSEL								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x48))      /* �˿�PG�������üĴ��� */
#define REG_SCU_PADADS								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x54))		/* �˿���ģ���üĴ��� */
#define REG_SCU_PADADS1								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x58))		/* �˿���ģ���üĴ��� */	
#define REG_SCU_PADDR0								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x60))		/* �˿������������üĴ���0 */
#define REG_SCU_PADDR1								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x64))      /* �˿������������üĴ���1 */
#define REG_SCU_PADPU0								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x6C))		/* �˿��������üĴ���0 */
#define REG_SCU_PADPU1								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x70))      /* �˿��������üĴ���1 */
#define REG_SCU_PADPD0								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x78))		/* �˿��������üĴ���0 */
#define REG_SCU_PADPD1								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x7C))      /* �˿��������üĴ���1 */
#define REG_SCU_PADOD0								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x84))		/* �˿ڿ�©������üĴ���0 */
#define REG_SCU_PADOD1								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x88))      /* �˿ڿ�©������üĴ���1 */
#define REG_SCU_PADCS0								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x90))		/* �˿������������üĴ���0 */
#define REG_SCU_PADCS1								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x94))      /* �˿������������üĴ���1 */
#define REG_SCU_PADIE0								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0x9C))		/* �˿��������üĴ���0 */
#define REG_SCU_PADIE1								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xA0))      /* �˿��������üĴ���1 */
#define REG_SCU_PADSR0								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xA8))      /* �˿��������üĴ���0 */
#define REG_SCU_PADSR1								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xAC))      /* �˿��������üĴ���1 */
#define REG_SCU_IOCTRLPROTECT						(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xB4))		/* IO���Ʊ����Ĵ��� */
#define REG_SCU_LVDCFG								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xB8))		/* LVD���ƼĴ��� */
#define REG_SCU_OPACFG								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xBC))      /* OPA���ƼĴ��� */
#define REG_SCU_CMPCFG								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xC0))      /* CMP���ƼĴ��� */
#define REG_SCU_EXTRSTSEL							(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xC4))		/* �ⲿ��λ�˿�ѡ��Ĵ��� */
#define REG_SCU_STOPMODESEL							(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xC8))		/* ֹͣģʽѡ��Ĵ��� */
#define REG_SCU_REMAP								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xCC))		/* REMAP�Ĵ��� */
#define REG_SCU_VECTOROFFSET						(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xD0))		/* �ж�������ַ��ӳ��Ĵ��� */
#define REG_SCU_RNGCR								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xD4))		/* ��������ƼĴ��� */
#define REG_SCU_RNGSEED								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xD8))		/* ��������ӼĴ��� */
#define REG_SCU_RNGDATA								(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xDC))		/* ��������ݼĴ��� */	
#define REG_SCU_BUZZERCR							(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xE0))		/* ���������ƼĴ���/BUZERCR */
#define REG_SCU_LVRCFG							    (*(volatile uint32_t *)(SCU_BASE_ADDR + 0xE4))      /* LVR���ƼĴ��� */
#define REG_SCU_VREFCFG							    (*(volatile uint32_t *)(SCU_BASE_ADDR + 0xE8))      /* VREF���ƼĴ��� */
#define REG_SCU_XTHCFG						        (*(volatile uint32_t *)(SCU_BASE_ADDR + 0xEC))      /* XTH���ƼĴ��� */
#define REG_SCU_COMPINEN						    (*(volatile uint32_t *)(SCU_BASE_ADDR + 0xF0))		/* �Ƚ���״̬�Ĵ��� */
#define REG_SCU_ANALOGSTATUS						(*(volatile uint32_t *)(SCU_BASE_ADDR + 0xF4))		/* ģ��״̬�Ĵ��� */	
#define REG_SCU_VREFSTATUS					        (*(volatile uint32_t *)(SCU_BASE_ADDR + 0xF8))      /* VREF״̬�Ĵ��� */ 
    
/*------------------------------------------------- WDT ---------------------------------------------------*/
#define WDT_BASE_ADDR								0x40002400
#define REG_WDT_LOAD								(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x00))			/* WDT װ�ؼĴ��� */
#define REG_WDT_CNT									(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x04))			/* WDT �����Ĵ��� */
#define REG_WDT_CTRL								(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x08))			/* WDT ���ƼĴ��� */
#define REG_WDT_CLR									(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x0C))			/* WDT ����Ĵ��� */
#define REG_WDT_INTRAW								(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x10))			/* WDT RAW�ж�״̬�Ĵ��� */
#define REG_WDT_MINTS								(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x14))			/* WDT MASK�ж�״̬�Ĵ��� */
#define REG_WDT_STALL								(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x18))			/* WDT STALL�Ĵ��� */
#define REG_WDT_LOCK								(*(volatile uint32_t *)(WDT_BASE_ADDR + 0x1C))			/* WDT LOCK�Ĵ��� */

/*------------------------------------------------- LPTIMER23 -----------------------------------------------*/
#define LPTIMER23_BASE_ADDR							0x40002800
#define REG_LPTIM2_CR1								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x00))		/* LPTIM2 ���ƼĴ���1 */
#define REG_LPTIM2_CR2								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x04))		/* LPTIM2 ���ƼĴ���2 */
#define REG_LPTIM23_IER								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x08))		/* LPTIM23 �ж�ʹ�ܼĴ��� */
#define REG_LPTIM23_SR								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x0C))		/* LPTIM23 �жϱ�־�Ĵ��� */
#define REG_LPTIM2_CNT1								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x10))		/* LPTIM2 ����ֵ�Ĵ��� */
#define REG_LPTIM2_CCMCFG1							(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x14))		/* LPTIM2 ��׽�Ƚ����üĴ���1 */
#define REG_LPTIM2_CCMCFG2							(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x18))		/* LPTIM2 ��׽�Ƚ����üĴ���2 */
#define REG_LPTIM2_ARR1								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x1C))		/* LPTIM2 �Զ���װ�ؼĴ��� */
#define REG_LPTIM2_CCR1								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x20))		/* LPTIM2 ��׽�ȽϼĴ���1 */
#define REG_LPTIM2_CCR2								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x24))		/* LPTIM2 ��׽�ȽϼĴ���2 */
#define REG_LPTIM2_LOAD1							(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x28))		/* LPTIM2 ����ֵload�Ĵ��� */
#define REG_LPTIM2_BUFFER1							(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x2C))		/* LPTIM2 ��������Ĵ��� */
#define REG_LPTIM3_CR3								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x30))		/* LPTIM3 ���ƼĴ���1 */
#define REG_LPTIM3_CR4								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x34))		/* LPTIM3 ���ƼĴ���2 */
#define REG_LPTIM3_CNT2								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x38))		/* LPTIM3 �ж�ʹ�ܼĴ��� */
#define REG_LPTIM3_CCMCFG3							(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x3C))		/* LPTIM3 �жϱ�־�Ĵ��� */
#define REG_LPTIM3_CCMCFG4							(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x40))		/* LPTIM3 ����ֵ�Ĵ��� */
#define REG_LPTIM3_ARR2								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x44))		/* LPTIM3 ��׽�Ƚ����üĴ���1 */
#define REG_LPTIM3_CCR3								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x48))		/* LPTIM3 ��׽�Ƚ����üĴ���2 */
#define REG_LPTIM3_CCR4								(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x4C))		/* LPTIM3 �Զ���װ�ؼĴ��� */
#define REG_LPTIM3_LOAD2							(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x50))		/* LPTIM3 ����ֵload�Ĵ��� */
#define REG_LPTIM3_BUFFER2							(*(volatile uint32_t *)(LPTIMER23_BASE_ADDR + 0x54))		/* LPTIM3 ��������Ĵ��� */
	
/*------------------------------------------------- BTIMER01 ---------------------------------------------------*/
#define	BTIM01_BASE_ADDR     						0x40002C00
#define REG_BTIM0_CR								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x00))			/*BSTIM0���ƼĴ���*/
#define	REG_BTIM01_DIER								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x04))			/*BSTIM01�ж�ʹ�ܼĴ���*/
#define	REG_BTIM01_SR								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x08))			/*BSTIM01״̬�Ĵ���*/			
#define	REG_BTIM0_EGR								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x0C))			/*BSTIM0�¼������Ĵ���*/	
#define	REG_BTIM0_CNT								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x10))			/*BSTIM0�������Ĵ���*/
#define	REG_BTIM0_PSC								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x14))			/*BSTIM0Ԥ��Ƶ�Ĵ���*/
#define	REG_BTIM0_ARR								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x18))			/*BSTIM0�Զ����ؼĴ���*/
#define	REG_BTIM0_CCR								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x1C))			/*BSTIM0�ȽϼĴ���*/
#define	REG_BTIM1_CR								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x20))			/*BSTIM1���ƼĴ���*/
#define	REG_BTIM1_EGR								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x24))			/*BSTIM1�¼������Ĵ���*/
#define	REG_BTIM1_CNT								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x28))			/*BSTIM1�������Ĵ���*/
#define	REG_BTIM1_PSC								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x2C))			/*BSTIM1Ԥ��Ƶ�Ĵ���*/
#define	REG_BTIM1_ARR								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x30))			/*BSTIM1�Զ����ؼĴ���*/
#define	REG_BTIM1_CCR								(*(volatile uint32_t *)(BTIM01_BASE_ADDR + 0x34))			/*BSTIM1�ȽϼĴ���*/

/*------------------------------------------------- UART1 -------------------------------------------------*/
#define UART1_BASE_ADDR								0x40003000
#define REG_UART1_RBR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x00))	/* UART1 ���ջ���Ĵ��� */
#define REG_UART1_THR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x00))	/* UART1 ���ͻ���Ĵ��� */
#define REG_UART1_DLL								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x00))	/* UART1 �����ʷ�Ƶ��λ�Ĵ��� */	
#define REG_UART1_DLH								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x04))	/* UART1 �����ʷ�Ƶ��λ�Ĵ��� */
#define REG_UART1_IER								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x04))	/* UART1 �ж�ʹ�ܼĴ��� */
#define REG_UART1_IIR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x08))	/* UART1 �ж�״̬�Ĵ��� */
#define REG_UART1_FCR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x08))	/* UART1 FIFO���ƼĴ��� */
#define REG_UART1_LCR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x0C))	/* UART1 LINE���ƼĴ��� */
#define REG_UART1_MCR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x10))	/* UART1 �����ƼĴ��� */
#define REG_UART1_LSR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x14))	/* UART1 LINE�ж�״̬�Ĵ��� */
#define REG_UART1_MSR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x18))	/* UART1 ��״̬�Ĵ��� */	
#define REG_UART1_USR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x7C))	/* UART1 ״̬�Ĵ��� */
#define REG_UART1_TFL								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x80))	/* UART1 ����FIFO���ݸ����Ĵ��� */	
#define REG_UART1_RFL								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0x84))	/* UART1 ����FIFO���ݸ����Ĵ��� */	
#define REG_UART1_DLF								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0xC0))	/* UART1 С����Ƶ�Ĵ��� */
#define REG_UART1_RAR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0xC4))	/* UART1 ���յ�ַƥ��Ĵ��� */
#define REG_UART1_TAR								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0xC8))	/* UART1 ���͵�ַƥ��Ĵ��� */
#define REG_UART1_LCRE								(*(volatile uint32_t *)(UART1_BASE_ADDR + 0xCC))	/* UART1 LINE������չ�Ĵ��� */

/*------------------------------------------------- GTIMER1 ------------------------------------------------*/
#define GTIMER1_BASE_ADDR							0x40003400
#define REG_GTIM1_CR								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x00))	/* Timer1 ���ƼĴ��� */	
#define REG_GTIM1_IER								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x04))	/* Timer1 �ж�ʹ�ܼĴ��� */
#define REG_GTIM1_SR								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x08))	/* Timer1 ״̬�Ĵ��� */
#define REG_GTIM1_EGR								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x0C))	/* Timer1 �¼������Ĵ��� */
#define REG_GTIM1_CCMR								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x10))	/* Timer1 ��׽/�ȽϼĴ��� */
#define REG_GTIM1_CCER								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x14))	/* Timer1 ��׽/�Ƚ�ʹ�ܼĴ��� */
#define REG_GTIM1_CNT								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x18))	/* Timer1 �������Ĵ��� */
#define REG_GTIM1_PSC								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x1C))	/* Timer1 Ԥ��Ƶ�Ĵ��� */
#define REG_GTIM1_ARR								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x20))	/* Timer1 �Զ����ؼĴ��� */
#define REG_GTIM1_CCR								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x24))	/* Timer1 ��׽/�ȽϼĴ��� */
#define REG_GTIM1_CARS1								(*(volatile uint32_t *)(GTIMER1_BASE_ADDR + 0x28))	/* Timer1 ��׽/�ȽϼĴ��� */ 
	
/*------------------------------------------------- GTIMER2 ------------------------------------------------*/
#define GTIMER2_BASE_ADDR							0x40003800
#define REG_GTIM2_CR								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x00))	/* Timer2 ���ƼĴ��� */	
#define REG_GTIM2_IER								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x04))	/* Timer2 �ж�ʹ�ܼĴ��� */
#define REG_GTIM2_SR								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x08))	/* Timer2 ״̬�Ĵ��� */
#define REG_GTIM2_EGR								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x0C))	/* Timer2 �¼������Ĵ��� */
#define REG_GTIM2_CCMR								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x10))	/* Timer2 ��׽/�ȽϼĴ��� */
#define REG_GTIM2_CCER								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x14))	/* Timer2 ��׽/�Ƚ�ʹ�ܼĴ��� */
#define REG_GTIM2_CNT								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x18))	/* Timer2 �������Ĵ��� */
#define REG_GTIM2_PSC								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x1C))	/* Timer2 Ԥ��Ƶ�Ĵ��� */
#define REG_GTIM2_ARR								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x20))	/* Timer2 �Զ����ؼĴ��� */
#define REG_GTIM2_CCR								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x24))	/* Timer2 ��׽/�ȽϼĴ��� */
#define REG_GTIM2_CARS1								(*(volatile uint32_t *)(GTIMER2_BASE_ADDR + 0x28))	/* Timer2 ��׽/�ȽϼĴ��� */ 
	
/*------------------------------------------------- WWDT ------------------------------------------------*/
#define WWDT_BASE_ADDR								0x40003C00
#define REG_WWDT_CON								(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x00))		/* WWDT���ƼĴ��� */
#define REG_WWDT_CFG								(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x04))		/* WWDT���üĴ��� */
#define REG_WWDT_CNT								(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x08))		/* WWDT�����Ĵ��� */
#define REG_WWDT_IE									(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x0C))		/* WWDT�ж�ʹ�ܼĴ��� */
#define REG_WWDT_IF									(*(volatile uint32_t *)(WWDT_BASE_ADDR + 0x10))		/* WWDT�жϱ�־�Ĵ��� */
	
/*------------------------------------------------- GPIO --------------------------------------------------*/
#define GPIOA										0
#define GPIOB										1
#define GPIOC										2
#define GPIOD										3
#define GPIOE										4
#define GPIOF										8
#define GPIOG										9
#define GPIO_BASE_ADDR(x)							(0x40004000 + 0x0400 * (x))
#define REG_GPIO_DIR(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x00))	/* GPIO ���ݷ���Ĵ��� */
#define REG_GPIO_SET(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x08))	/* GPIO �����λ�Ĵ��� */
#define REG_GPIO_CLR(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x0C))	/* GPIO �������Ĵ��� */
#define REG_GPIO_ODATA(x)							(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x10))	/* GPIO �������ӳ��Ĵ��� */
#define REG_GPIO_IDATA(x)							(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x14))	/* GPIO ��������ӳ��Ĵ��� */
#define REG_GPIO_IEN(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x18))	/* GPIO �ж�ʹ�ܼĴ��� */
#define REG_GPIO_IS(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x1C))	/* GPIO �жϴ���ģʽ�Ĵ��� */
#define REG_GPIO_IBE(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x20))	/* GPIO �жϴ���ģʽ�Ĵ��� */
#define REG_GPIO_IEV(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x24))	/* GPIO �жϴ���ģʽ�Ĵ��� */
#define REG_GPIO_IC(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x28))	/* GPIO �ж�״̬����Ĵ��� */
#define REG_GPIO_RIS(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x2C))	/* GPIO ԭʼ�ж�״̬�Ĵ��� */
#define REG_GPIO_MIS(x)								(*(volatile uint32_t *)(GPIO_BASE_ADDR(x) + 0x30))	/* GPIO ���κ��ж�״̬�Ĵ��� */

/*------------------------------------------------- I2C ---------------------------------------------------*/
#define I2C_BASE_ADDR								0x40005400
#define REG_I2C_CR                  				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x00))		/* I2C ���üĴ��� */
#define REG_I2C_CLR                 				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x04))		/* I2C ��������Ĵ��� */
#define REG_I2C_STAT                				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x08))		/* I2C ״̬�Ĵ��� */
#define REG_I2C_DATA                				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x0C))		/* I2C ���ݼĴ��� */
#define REG_I2C_CCR                 				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x10))		/* I2C ���������üĴ��� */
#define REG_I2C_SAD0                				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x14))		/* I2C SLAVE��ַ�Ĵ���0 */
#define REG_I2C_SADM0               				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x18))		/* I2C SLAVE��ַ���μĴ���0 */
#define REG_I2C_XSAD0               				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x1C))		/* I2C SLAVE ��չ��ַ�Ĵ��� */
#define REG_I2C_XSADM0              				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x20))		/* I2C SLAVE ��չ��ַ���μĴ��� */
#define REG_I2C_SRST                				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x24))		/* I2C ��λ�Ĵ��� */
#define REG_I2C_SAD1                				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x28))		/* I2C SLAVE��ַ�Ĵ���1 */
#define REG_I2C_SADM1               				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x2C))		/* I2C SLAVE��ַ���μĴ���1 */
#define REG_I2C_SAD2                				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x30))		/* I2C SLAVE��ַ�Ĵ���2 */
#define REG_I2C_SADM2               				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x34))		/* I2C SLAVE��ַ���μĴ���2 */
#define REG_I2C_SAD3                				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x38))		/* I2C SLAVE��ַ�Ĵ���3 */
#define REG_I2C_SADM3               				(*(volatile uint32_t *)(I2C_BASE_ADDR + 0x3C))		/* I2C SLAVE��ַ���μĴ���3 */
	
/*------------------------------------------------- SPI1 --------------------------------------------------*/
#define SPI1_BASE_ADDR								0x40005800
#define REG_SPI1_SPICR          					(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x00))		/* SPI1 ���üĴ��� */
#define REG_SPI1_SPICS0            					(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x04))		/* SPI1 ��ģʽ���ƼĴ���0 */
#define REG_SPI1_SPICS1            					(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x08))		/* SPI1 ��ģʽ���ƼĴ���1 */
#define REG_SPI1_SPIOPCR            				(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x14))		/* SPI1 ���̿��ƼĴ��� */
#define REG_SPI1_SPIIE          					(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x18))		/* SPI1 �жϿ��ƼĴ��� */
#define REG_SPI1_SPIIF          					(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x1c))		/* SPI1 �жϱ�־�Ĵ��� */
#define REG_SPI1_SPITXBUF           				(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x20))		/* SPI1 ���ջ���Ĵ��� */
#define REG_SPI1_SPIRXBUF           				(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x24))		/* SPI1 ���ջ���Ĵ��� */
#define REG_SPI1_DMA_SPIRX_LEV      				(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x28))		/* SPI1 DMA�������üĴ��� */
#define REG_SPI1_DMA_SPITX_LEV      				(*(volatile uint32_t *)(SPI1_BASE_ADDR + 0x2C))		/* SPI1 DMA�������üĴ��� */

/*------------------------------------------------- CAN ---------------------------------------------------*/
#define CAN_BASE_ADDR								0x40005C00 
#define REG_CAN_MR									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x00))		/* ģʽ�Ĵ���*/
#define REG_CAN_CMR									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x04))		/* ָ��Ĵ���*/
#define REG_CAN_SR									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x08))		/* ���ƼĴ���*/
#define REG_CAN_ISR									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x0C))		/* �ж�״̬�Ĵ���*/
#define REG_CAN_IMR									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x10))		/* �ж�ʹ�ܼĴ���*/
#define REG_CAN_RMC									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x14))		/* ����FIFO���ݸ����Ĵ���*/
#define REG_CAN_BTR0								(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x18))		/* ����ʱ��Ĵ���0*/
#define REG_CAN_BTR1								(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x1C))		/* ����ʱ��Ĵ���1*/
#define REG_CAN_TXBUF								(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x20))		/* ���ͻ���Ĵ���*/
#define REG_CAN_RXBUF								(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x24))		/* ���ջ���Ĵ���*/
#define REG_CAN_ACR									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x28))		/* ���չ���ƥ��Ĵ���*/
#define REG_CAN_AMR									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x2C))		/* ���չ������μĴ���*/
#define REG_CAN_ECC									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x30))		/* �����벶׽�Ĵ���*/
#define REG_CAN_RXERR								(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x34))		/* ���մ�������Ĵ���*/
#define REG_CAN_TXERR								(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x38))		/* ���ʹ���Ĵ���*/
#define REG_CAN_ALC									(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x3C))		/* �ٲö�ʧ����Ĵ���*/
#define REG_CAN_RXADDR								(*(volatile uint32_t *)(CAN_BASE_ADDR + 0x40))		/* ���ջ������ַ���üĴ���*/

/*------------------------------------------------- UART2 -------------------------------------------------*/
#define UART2_BASE_ADDR								0x40006800
#define REG_UART2_ISR								(*(volatile uint32_t *)(UART2_BASE_ADDR + 0x00))	/* UART2 �ж�״̬�Ĵ��� */
#define REG_UART2_IER								(*(volatile uint32_t *)(UART2_BASE_ADDR + 0x04))	/* UART2 �ж�ʹ�ܼĴ��� */
#define REG_UART2_CR								(*(volatile uint32_t *)(UART2_BASE_ADDR + 0x08))	/* UART2 ���ƼĴ��� */
#define REG_UART2_TDR								(*(volatile uint32_t *)(UART2_BASE_ADDR + 0x0C))	/* UART2 �������ݼĴ��� */
#define REG_UART2_RDR								(*(volatile uint32_t *)(UART2_BASE_ADDR + 0x0C))	/* UART2 �������ݼĴ��� */
#define REG_UART2_BRPL								(*(volatile uint32_t *)(UART2_BASE_ADDR + 0x10))	/* UART2 �����ʲ�����λ�Ĵ��� */
#define REG_UART2_BRPH								(*(volatile uint32_t *)(UART2_BASE_ADDR + 0x14))	/* UART2 �����ʲ�����λ�Ĵ��� */

/*------------------------------------------------- I2C1 ---------------------------------------------------*/
#define I2C1_BASE_ADDR								0x40006C00
#define REG_I2C1_CR                  				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x00))		/* I2C ���üĴ��� */
#define REG_I2C1_CLR                 				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x04))		/* I2C ��������Ĵ��� */
#define REG_I2C1_STAT                				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x08))		/* I2C ״̬�Ĵ��� */
#define REG_I2C1_DATA                				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x0C))		/* I2C ���ݼĴ��� */
#define REG_I2C1_CCR                 				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x10))		/* I2C ���������üĴ��� */
#define REG_I2C1_SAD0                				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x14))		/* I2C SLAVE��ַ�Ĵ���0 */
#define REG_I2C1_SADM0               				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x18))		/* I2C SLAVE��ַ���μĴ���0 */
#define REG_I2C1_XSAD0               				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x1C))		/* I2C SLAVE ��չ��ַ�Ĵ��� */
#define REG_I2C1_XSADM0              				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x20))		/* I2C SLAVE ��չ��ַ���μĴ��� */
#define REG_I2C1_SRST                				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x24))		/* I2C ��λ�Ĵ��� */
#define REG_I2C1_SAD1                				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x28))		/* I2C SLAVE��ַ�Ĵ���1 */
#define REG_I2C1_SADM1               				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x2C))		/* I2C SLAVE��ַ���μĴ���1 */
#define REG_I2C1_SAD2                				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x30))		/* I2C SLAVE��ַ�Ĵ���2 */
#define REG_I2C1_SADM2               				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x34))		/* I2C SLAVE��ַ���μĴ���2 */
#define REG_I2C1_SAD3                				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x38))		/* I2C SLAVE��ַ�Ĵ���3 */
#define REG_I2C1_SADM3               				(*(volatile uint32_t *)(I2C1_BASE_ADDR + 0x3C))		/* I2C SLAVE��ַ���μĴ���3 */

/*------------------------------------------------- BTIMER23 ---------------------------------------------------*/
#define	BTIM23_BASE_ADDR     						0x40007000
#define REG_BTIM2_CR								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x00))			/*BSTIM2���ƼĴ���*/
#define	REG_BTIM23_DIER								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x04))			/*BSTIM23�ж�ʹ�ܼĴ���*/
#define	REG_BTIM23_SR								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x08))			/*BSTIM23״̬�Ĵ���*/			
#define	REG_BTIM2_EGR								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x0C))			/*BSTIM2�¼������Ĵ���*/	
#define	REG_BTIM2_CNT								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x10))			/*BSTIM2�������Ĵ���*/
#define	REG_BTIM2_PSC								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x14))			/*BSTIM2Ԥ��Ƶ�Ĵ���*/
#define	REG_BTIM2_ARR								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x18))			/*BSTIM2�Զ����ؼĴ���*/
#define	REG_BTIM2_CCR								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x1C))			/*BSTIM2�ȽϼĴ���*/
#define	REG_BTIM3_CR								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x20))			/*BSTIM3���ƼĴ���*/
#define	REG_BTIM3_EGR								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x24))			/*BSTIM3�¼������Ĵ���*/
#define	REG_BTIM3_CNT								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x28))			/*BSTIM3�������Ĵ���*/
#define	REG_BTIM3_PSC								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x2C))			/*BSTIM3Ԥ��Ƶ�Ĵ���*/
#define	REG_BTIM3_ARR								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x30))			/*BSTIM3�Զ����ؼĴ���*/
#define	REG_BTIM3_CCR								(*(volatile uint32_t *)(BTIM23_BASE_ADDR + 0x34))			/*BSTIM3�ȽϼĴ���*/
	
/*------------------------------------------------- ATIMER ---------------------------------------------------*/
#define ATIM_BASE_ADDR								0x40007400 
#define REG_ATIM_CR1								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x00))				/* ATIM���ƼĴ���1 */
#define REG_ATIM_CR2								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x04))				/* ATIM���ƼĴ���2 */
#define REG_ATIM_SMCR								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x08))				/* ATIM�ӻ�ģʽ���ƼĴ��� */	
#define REG_ATIM_DIER								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x0C))				/* ATIM DMA���ж�ʹ�ܼĴ��� */
#define REG_ATIM_SR									(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x10))				/* ATIM״̬�Ĵ��� */
#define REG_ATIM_EGR								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x14))				/* ATIM�¼������Ĵ��� */
#define REG_ATIM_CCMR1								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x18))				/* ATIM��׽/�Ƚ�ģʽ�Ĵ���1 */
#define REG_ATIM_CCMR2								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x1C))				/* ATIM��׽/�Ƚ�ģʽ�Ĵ���2 */
#define REG_ATIM_CCER								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x20))				/* ATIM��׽/�Ƚ�ʹ�ܼĴ���*/
#define REG_ATIM_CNT								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x24))				/* ATIM�������Ĵ���*/
#define REG_ATIM_PSC								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x28))				/* ATIMԤ��Ƶ�Ĵ���*/	
#define REG_ATIM_ARR								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x2C))				/* ATIM�Զ����ؼĴ���*/	
#define REG_ATIM_RCR								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x30))				/* ATIM�ظ������Ĵ���*/	
#define REG_ATIM_CCR1								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x34))				/* ATIM��׽/�ȽϼĴ���1*/	
#define REG_ATIM_CCR2								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x38))				/* ATIM��׽/�ȽϼĴ���2*/	
#define REG_ATIM_CCR3								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x3C))				/* ATIM��׽/�ȽϼĴ���3*/	
#define REG_ATIM_CCR4								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x40))				/* ATIM��׽/�ȽϼĴ���4*/	
#define REG_ATIM_BDTR								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x44))				/* ATIMɲ�����������ƼĴ���*/
#define REG_ATIM_DCR								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x48))				/* ATIM DMA���ƼĴ���*/	
#define REG_ATIM_DMAR								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x4C))				/* ATIM DMA���ʼĴ���*/	
#define REG_ATIM_BKCTL								(*(volatile uint32_t *)(ATIM_BASE_ADDR + 0x60))				/* ATIM ɲ��������ƼĴ���*/	

/*------------------------------------------------- DMA ---------------------------------------------------*/
#define DMA_Channel_0   0
#define DMA_Channel_1   1
#define DMA_Channel_2   2
#define DMA_Channel_3   3
#define DMA_Channel_4   4
#define DMA_Channel_5   5
#define DMA_Channel_6   6
#define DMA_Channel_7   7
#define DMA_BASE_ADDR(x)							(0x40020000 + 0x20 * (x))	
#define REG_DMA_SRCADDRC(x)							(*(volatile uint32_t *)(DMA_BASE_ADDR(x) + 0x00))	/* ͨ��0Դ��ַ�Ĵ��� */
#define REG_DMA_DSTADDRC(x)							(*(volatile uint32_t *)(DMA_BASE_ADDR(x) + 0x04))	/* ͨ��0Ŀ�ĵ�ַ�Ĵ��� */
#define REG_DMA_CHCTRLC(x)							(*(volatile uint32_t *)(DMA_BASE_ADDR(x) + 0x08))	/* ͨ��0������Ϣ�Ĵ��� */
#define REG_DMA_CHSTSC(x)							(*(volatile uint32_t *)(DMA_BASE_ADDR(x) + 0x0C))	/* ͨ��0����״̬�Ĵ��� */
#define REG_DMA_CHSPERC(x)                      	(*(volatile uint32_t *)(DMA_BASE_ADDR(x) + 0x10))	/* ͨ��0Դ����ѡ��Ĵ��� */
#define REG_DMA_CHDPERC(x)                      	(*(volatile uint32_t *)(DMA_BASE_ADDR(x) + 0x14))	/* ͨ��0Դ����ѡ��Ĵ��� */	
#define REG_DMA_EN									(*(volatile uint32_t *)(DMA_BASE_ADDR(0) + 0x100))		/* DMA������ʹ�� */
#define REG_DMA_SOFTRESET							(*(volatile uint32_t *)(DMA_BASE_ADDR(0) + 0x104))		/* DMA����λ */
#define REG_DMA_INTSTATUS							(*(volatile uint32_t *)(DMA_BASE_ADDR(0) + 0x108))		/* DMA�ж�ָʾ�Ĵ��� */	
#define REG_DMA_INTMASK							    (*(volatile uint32_t *)(DMA_BASE_ADDR(0) + 0x10C))		/* DMA�ж����μĴ��� */
#define REG_DMA_BASICINFM							(*(volatile uint32_t *)(DMA_BASE_ADDR(0) + 0x110))		/* DMA������Ϣ */
#define REG_DMA_PERREQ								(*(volatile uint32_t *)(DMA_BASE_ADDR(0) + 0x114))		/* DMA����������Ϣ */	
	
/*------------------------------------------------- CACHE ---------------------------------------------------*/
#define CACHE_BASE_ADDR								0x20004400
#define REG_CACHE_CACR								(*(volatile uint32_t *)(CACHE_BASE_ADDR))

/*------------------------------------------------- System Tick -------------------------------------------*/
#define SYSTICK_BASE_ADDR							0xE000E010
#define REG_SYSTICK_CSR          					(*(volatile uint32_t *)(SYSTICK_BASE_ADDR + 0x00))	/* SysTick���ƺ�״̬�Ĵ��� */
#define REG_SYSTICK_RVR          					(*(volatile uint32_t *)(SYSTICK_BASE_ADDR + 0x04))	/* SysTick����ֵ�Ĵ��� */
#define REG_SYSTICK_CVR          					(*(volatile uint32_t *)(SYSTICK_BASE_ADDR + 0x08))	/* SysTick��ǰֵ�Ĵ��� */

#endif
